Testability in integrated circuit devices (ICs) generally refers to an ability of test equipment (TE), usually externally connected to an IC, to access circuit blocks within the IC for testing and debugging (troubleshooting) purposes. Typically, during a testing or debugging process, the TE, which may be connected to the IC through an IC input/output (I/O) interface, and more frequently through test pins on the IC, access one or more circuit blocks by overriding or bypassing control circuitry in the IC. Once the circuit block is accessed, the TE connects to the block, occasionally bypassing other blocks in the IC, and may perform functions which may include configuring, initializing, triggering, and/or operating the circuit block. Optionally, the TE may be connected to a connector of a printed circuit board (PCB), or of an electronic module, comprising a plurality of ICs, the TE adapted to test the circuit blocks in each IC.
JTAG, or Joint Test Action Group, was an industry group formed in the mid-1980's to examine problems associated with testing printed circuit boards (PCBs) due to limited access to circuit blocks inside the PCB. JTAG was also responsible to propose solutions for solving the limited access problem. The solution was first documented in 1990 as an industry standard of the Institute of Electrical and Electronic Engineers, IEEE 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture. Since then this standard, either in the original form and/or in any, or all, of the revised updated forms, has been adopted by many IC manufacturers, the architecture described therein frequently used as a primary means to access circuit blocks in ICs.
The IEEE 1149.1 boundary scan architecture is based on connecting a memory cell to every signal input and every signal output inside a device, and serially connecting the memory cells together to form a parallel-in, parallel-out shift register. Data from the TE is input to the IC through a pin on the device generally identified as Test Data In (TDI), and is shifted from memory cell to memory cell until reaching a second pin on the device, Test Data Out (TDO), through which the data is output back to the TE. Optionally, the data from TDO may be used as an input to the TDI of a second IC. The TE may then compare the data input with the data output. A clock signal from the TE is provided through a third pin on the device, Test Clock (TCK). Modes of operation of the circuit block are provided by the TE through a fourth pin on the device, Test Mode Select (TMS). An optional fifth pin on the device, Test Reset (TRST) may be used to connect the TE for resetting a Test Access Port (TAP) controller in the device. More information on the boundary scan architecture may be found in IEEE 1149.1-2001, incorporated herein by reference in its entirety.